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Title Raptor Codes: The Implementation Point of View
Degree Ph.D.
Author Todor Mladenov
Advisor Kiseon Kim
Graduation Date 2011.08.24 File
    Date 2013-09-11 16:11

Raptor codes have been proven very suitable for mobile broadcast and multicast

multimedia content delivery, and yet their computational complexity has not been in-

vestigated in the context of embedded systems. At the heart of Raptor codes are the

matrix inversion and vector decoder operations. This Thesis work at rst analyzes the

performance, energy pro le and resource implication of two matrix inversion and de-

coding algorithms; Gaussian elimination (GE) and 3rd Generation Partnership Group

(3GPP) Multimedia Broadcast/Multicast Services (MBMS) standard inactivation de-

coding Gaussian elimination (IDGE), for the Raptor decoder on a system on a chip

(SoC) platform with a soft-core embedded processor. The effect of the cache size, mem-

ory type and mapping on the performance of the two algorithms under consideration

are investigated. The work shows that with an appropriate data to memory mapping

a speed up factor of 5:77 can be obtained for GE with respect to IDGE. Furthermore,

a dedicated peripheral hardware block is proposed that achieves 5:90 times better per-

formance compared with the software, requiring an energy consumption that is lower

by a factor of 5:5, when the symbol size and the data path word-length is small (32

bits). The Thesis work further shows that with parallel processing in hardware, using

the wider word-lengths, and employing bigger symbol sizes T, the performance can

be improved, while reducing the energy consumption. Extending the hardware word-

length and symbol size T to 128 bits will results in a performance improvement factor

of 6:73 in favor of the hardware; while energy consumption reduces by a factor of 3:8!

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